(a) Field of the Invention
The present invention relates to a semiconductor memory device having a DRAM (dynamic random access memory) cell structure and handled as a SRAM (static random access memory).
(b) Description of the Related Art
Semiconductor memory devices which have a DRAM cell structure and operating as SRAMs in the specification as viewed from the outside now play an important role in improving the functions of cellular phones which have been developed rapidly in these days. The advantages of this type of semiconductor memory device (may be referred to as simply “memory device” hereinafter) are that a periodic refreshing control from outside the memory device for maintaining the data stored in the memory cells, as encountered in the DRAM, is not needed to thereby allow easy handling thereof, and that the memory device has a larger capacity compared to the SRAM due to the simple DRAM cell structure.
It is to be noted that the memory device requires in fact the refreshing operation for maintaining the data stored in the memory cells, because the memory device has DRAM cells in the memory cell array thereof. Nevertheless, due to the SRAM specification, the memory device has no refreshing control terminal for controlling the refreshing operation from outside the memory device. This necessitates the memory device to include therein a self refreshing control circuit for generating a refreshing request signal each time a refreshing time interval elapses.
The refreshing request signal for requesting the refreshing operation for the memory cells is delivered in the memory device at a refreshing cycle, which is calculated based on the data hold time of the memory cells. The refreshing request signal is delivered at any time of the processing in the memory device, and the stop of the refreshing operation after starting the refreshing operation may destroy stored data. Thus, some operation cycle of the memory device includes both the refreshing operation and a read/write operation for the input address supplied from outside the memory device. This makes it difficult to obtain a high operational speed in the memory device comparable to that of the SRAM which does not include the refreshing operation. It is desired that the memory device have larger capacity, lower operating voltage and higher-speed operation in view of the possible further development of the functions of the cellular phones.
FIG. 14 shows the conventional memory device (first conventional memory device) described in Patent Publication JP-A-2002-74944, and FIG. 15 shows a timing chart for the operation of the memory device of FIG. 14.
In the memory device of FIG. 14, an address transition detected signal (address transition signal) ATD is generated in response to a transition of the input address or a fall of the chip select signal /CS, followed by a refreshing operation in response to the address transition signal ATD and a successive read/write operation for the input address ADD supplied from outside the memory device.
Due to the refreshing operation performed before the read/write operation, it is sufficient that the input address ADD be fixed at the time of starting the read/write operation, which fact allows a considerable skew in the input address ADD. The term “skew” as used herein means a time interval between the time instant at which the first part of the input address ADD reaches the memory device and the time instant at which the last part of the input address ADD reaches the memory device to determine the input address ADD. It is to be noted that there arise a skew in the input address because a plurality of address lines transmit the input address ADD and have different transmission delays therethrough, and that the memory device starts for the read/write operation upon the delivery of the first part of the input signal and yet should perform the actual read/write operation after the delivery of the last part of the input signal.
In addition, the consecutive refreshing operation and read/write operation avoid a conflict between these operations to thereby avoid destruction of the stored data without delaying the start of the read/write operation. Further, there arises no conflict even if the write enable signal /WE is delayed during a write operation.
In a read operation for the input address, a one-shot pulse having a positive polarity (positive one-shot pulse) is generated in the address transition signal ATD, when the input address ADD changes with both the chip select signal /CS and the address latch signal LC being at a low level. If a refreshing request signal REF1 assumes a high level at this stage, a refreshing address R_ADD generated by a refreshing control circuit 4A is delivered to a multiplexer circuit 5 due to the high level of the address transition signal ATD; whereby the multiplexer circuit 5 delivers an internal address signal A_R1 as the selected address M_ADD. A row control circuit 13A delivers a positive one-shot pulse in a row enable signal RE.
The selected address M_ADD and the row address enable signal RE select the word address Ref_Word of the refreshing address, thereby starting the refreshing operation. More specifically, a read operation of the refreshing cycle is performed at the rising edge of the sense amplifier enable signal SE, followed by a rewrite operation of the refreshing cycle for the memory cell during the high level of the sense amplifier enable signal SE, After the rewrite operation is completed, a positive one-shot pulse is generated in a precharge enable signal PE to perform a precharge operation for the bit lines. Since the refreshing operation does not request output of data stored in the memory cells, a column enable signal CE stays at an inactive low level.
After the refreshing operation is completed, address transition signal ATD assumes a low level, and the address latch signal LC output from a latch control circuit 12 assumes a high level, whereby the input address ADD delivered from outside the memory device is latched. The latch timing of the input address ADD is set at the end of the refreshing cycle. This allows an address skew equivalent to the refreshing time interval to obviate any problem.
The latched input address L_ADD latched by the latch circuit 2 is delivered from the multiplexer circuit 5 as the selected address M_ADD. A positive one-shot pulse in the row enable signal RE selects the word address Nor-Word of the input address ADD to start a read operation, similarly to the refreshing operation. While setting the column enable signal CE at a high level, the read data from the input address ADD is delivered through the read/write bus WRB in response to the rising edge of the bit line selection signal Yj. The read data on the read/write bus WRB is then output through the I/O terminals in response to an output buffer enable signal CWO. It is to be noted that tAA shown in FIG. 15 represents the address access time.
If a trigger for generating the address transition signal ATD is not provided from outside the memory device within a specified delay time after refreshing request signal REF1 rises to a high level, a pulse generator circuit disposed in the refreshing control circuit 4A and activated by a rise of the delayed signal of refreshing request signal REF1 generates a negative one-shot pulse in refreshing request signal REF2. The fall of refreshing request signal REF2 allows the refreshing address “A_R1+1” generated by the refreshing control circuit 4A to be delivered from the multiplexer circuit 5 as the selected address M_ADD. On the other hand, a row control circuit 13A delivers a positive one-shot pulse in the row enable signal RE.
The word address Ref_Word of the refreshing address R_ADD is selected based on the selected address M_ADD and the row enable signal RE, thereby performing a refreshing operation. More specifically, a read operation is conducted in response to a rise of the sense amplifier enable signal SE, followed by a rewrite operation during the high level of the sense amplifier enable signal SE. After the rewrite operation is completed, a positive one-shot pulse is generated in the precharge enable signal PE for precharging the bit lines.
In the conventional memory device as described above, since the read operation is performed after waiting for the time length needed for completing the refreshing operation, the start of the read/write operation need not be delayed with respect to the timing of the address skew and the write enable signal /WE. However, there is a problem in the conventional memory device that the read time for the input address cannot be reduced.
The above patent publication also describes a second conventional memory device, which solves the above problem to thereby reduce the read time for the input address. In the second conventional memory device, a read operation for the input address is performed before the refreshing operation, while performing the refreshing operation before a write operation for the input address.
It is to be noted in the second conventional memory device that a judgement is essential as to whether the input address is directed to a read operation or a write operation before performing the refreshing operation. This necessitates provision of a time interval tAW_max between the address transition and the establishment of the write enable signal /WE. In other word, the judgement must be completed between the read operation and the write operation within the time interval set by tAW_max. Similarly, the start of the read operation must be determined in consideration of the skew (tskew) of the input address.
FIG. 16 shows a timing chart for the second conventional memory device in the refreshing operation and the read operation.
When the input address ADD is changed with both the chip select signal /CE and address latch signal LC being at a low level, a positive one-shot pulse is generated in the address transition signal ATD after the time length set by tAW_max or tskew elapses. Since the write enable signal /WE assumes an inactive high level, a read operation is started, wherein the input address ADD supplied from outside the memory device is latched by the address latch signal LC output from the latch control circuit 12.
Thereafter, the read operation for the input address is performed similarly to the first conventional memory device, delivering the read data through the I/O terminals. The refreshing operation for the refreshing address “A_R1” is performed after the completion of the read operation. In the, second conventional memory device, tAA as shown in FIG. 16 represents the address access time. In this case, if the time interval tAW_max and the skew (tskew) are set smaller than the refreshing time interval, the access time tAA is reduced compared to the first conventional memory device.
It is to be noted that the refreshing operation is started by refreshing control signal REF2, similarly to the first conventional memory device, if a trigger for generating the address transition signal ATD is not supplied from outside the memory device within a specified time length after refreshing control signal REF1 rises to a high level. If a read request signal is generated just after the refreshing operation is started, the refreshing operation cannot be stopped because the stop of the refreshing operation may cause a destruction of the data stored in the memory cell now subjected to the refreshing operation.
More specifically, if the refreshing operation is started in response to the change of the input address ADD etc. supplied from outside the memory device, the refreshing operation can be performed after the read operation. On the other hand, if the self-refreshing operation is started before the request of the read operation, the read operation cannot be performed until the refreshing operation is completed. Thus, the access time is equivalent to the case wherein the read operation is conducted after the refreshing operation is completed in the first conventional memory device, and therefore cannot be reduced in fact. In addition, there may be a waste of the operating time because both the refreshing operation and read/write operation cannot be performed during the time interval of tAW_max or tskew.
In view of the above, it is an object of the present invention to provide a semiconductor memory device of the type as described above and capable of operating at a higher speed.
The present invention provides a semiconductor memory device including: a memory cell array including a plurality of memory cells each having a DRAM cell structure; an input block for receiving an input address for a read/write operation from outside the memory device and generating an address transition signal upon receipt of the input address; a refreshing control circuit for controlling a refreshing cycle of the memory cell array, the refreshing control circuit generating a refreshing address for which data refreshing is to be performed; and a sense amplifier circuit for amplifying and reading/writing data from/into one of the memory cells specified by the input address or the refreshing address, the sense amplifier circuit including a temporary data memory for saving refreshing data read from the memory cells during the refreshing cycle, wherein the temporary data memory, saves the refreshing data if the address input block generates the address transition signal during the refreshing cycle.
The present invention also provides a method for controlling a semiconductor memory device having a DRAM cell structure, the method including the steps of: reading first data from a first memory cell specified by a refreshing address into a sense amplifier circuit in a refreshing cycle; responding to an input address to read/write second data in a second memory cell specified by the input address into the sense amplifier circuit after saving the first data therein; and writing the first data saved in the sense amplifier circuit into the first memory cell in the refreshing cycle.
In accordance with the semiconductor memory device and the method of the present invention, the access time of the read/write operation for the input address can be reduced due to the separation of the refreshing cycle into the read operation and the write operation of the refreshing cycle.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.